1. Field of the Invention
This invention relates to operation sequencing mechanisms. More particularly, it relates to data flow or distributed data processors.
2. Description of the Prior Art
The requirement for speed and efficiency of digital computing has increased over the years, and so has the complexity of digital computers increased. Switching speed has been increased to the point where incremental changes in such speeds does not provide the desired increases in the overall computing speed.
To substantially reduce the overall computing time, processors involving multiple operational or functional units have been designed. The functional units are intended to operate in parallel to thereby reduce the computing time. Such systems have been very successful but have suffered from extreme complexity and high cost.
Another prior art design that has greatly reduced overall computing time is that of the so-called pipeline computer where the computer is extremely fast in performing vector computations. However, highly sophisticated software is required to take advantage of the speed of these pipeline computers and in fact, there are certain classes of problems that are not efficiently run on such computers.
A relatively recent step forward in increasing speed of operation is that described in U.S. Pat. No. 3,962,706. The special purpose computer of that patent has an active memory that contains instructions and operands in so-called cells or instruction packets. No instruction is executed until its corresponding operands have been provided within its cell. A cell is made up of an instruction (specifies a functional unit and a specialized capability of that unit) and two operand registers. When the operands have been provided, the packet is sent to an arbitration unit and from there to the specified functional unit. From the functional unit, the resultant packet is sent to a distribution unit and back to the active memory. This type of specialized computer lends itself extremely well to small scale computers for doing specialized tasks such as fast Fourier transforms. Its distributed control, within the active memory, the arbitration unit, the distribution unit, etc., however, does not permit full scale implementation. A weather model, for example, which utilizes a million or more instructions is not feasibly capable of being implemented using this technique.
Another recent innovation is described in U.S. Pat. No. 3,978,452. The novelty described is in a plurality of function modules, each having its own arithmetic logic and memory. A module will not operate until all required inputs have been received by the module. It is a sophisticated technique, but requires a great deal of hardware. To reduce the hardware requirement, serial transmission and arithmetic is employed.
To overcome these disadvantages, the invention set out herein utilizes central control and a passive memory which can be extremely large. Also, the sequencing mechanism of this invention is adopted for use with a general purpose computer and is readily assembled from available integrated circuits.